The present invention relates to a charge transfer device for transferring information charge packet in predetermined units and converting the information charge packet to a voltage value to generate an image signal.
FIG. 1 is a schematic block diagram of a prior art imaging device 50. The imaging device 50 includes a CCD image sensor 1, a boosting circuit 2, a regulating circuit 3, a vertical driver circuit 4, a horizontal driver circuit 5, and a timing control circuit 6.
The CCD image sensor 1, which is, for example, a frame transfer type device, includes an imaging section 1i, a storage section 1s, a horizontal transfer section 1h, and an output section 1d. The imaging section 1i includes a plurality of vertical shift registers. Each bit of the vertical shift registers configures a light receiving pixel. The storage section 1s includes a plurality of vertical shift registers, which are connected continuously with the vertical shift registers of the imaging section 1i. The horizontal transfer section 1h includes a single shift register extending horizontally toward the output side of the storage section 1s. Each bit of the horizontal transfer section 1h receives the output of each vertical shift register of the storage section 1s. The output section 1d is arranged at the output side of the horizontal transfer section 1h. The output section 1d includes a floating diffusion, which functions as a capacitor for receiving the outputs in packet unit (e.g., for single pixel) of the horizontal transfer section 1h, and a reset drain, for retrieving and draining the charges stored in the floating diffusion.
The boosting circuit 2 is, for example, a charge pump boosting circuit. The boosting circuit 2 receives power supply voltage VD from an external device and boosts the power supply voltage VD. The boosted voltage is supplied to the CCD image sensor 1 and the vertical driver circuit 4. The boosting circuit 2 includes a positive voltage charge pump and a negative voltage charge pump (not shown). The positive voltage charge pump generates positive boosted voltage VOH, and the negative voltage charge pump generates negative boosted voltage VOL. The positive boosted voltage VOH is supplied to the substrate side of the CCD image sensor 1 as a substrate voltage. Further, the positive boosted voltage VOH is resistor-divided and supplied to the reset drain of the output section 1d as a reset voltage VR. The negative boosted voltage VOL is supplied to the vertical driver circuit 4 as a voltage that generates a transfer clock, which is used to perform vertical transfer.
The regulating circuit 3 receives the power supply voltage VD, generates a predetermined adjusted voltage VK, and supplies the horizontal driver circuit 5 with the adjusted voltage VK. In the regulating circuit 3, the voltage value of the adjusted voltage VK is set in accordance with the operational voltage of the horizontal driver circuit 5 in the next stage. The power supply voltage VD is lowered to the operational voltage of the horizontal driver circuit 5 to generate the adjusted voltage VK.
The vertical driver circuit 4 is operated when supplied with the boosted voltage VOL from the boosting circuit 2. The vertical driver circuit 4 generates a frame transfer clock signal Øf and a vertical transfer clock signal Øv, provides the frame transfer clock signal Øf to the imaging section 1i, and provides the vertical transfer clock signal Øv to the storage section 1s. The frame transfer clock signal Øf and the vertical transfer clock signal Øv are generated in synchronism with a vertical synchronization signal VT and a horizontal synchronization signal HT, which are generated by the timing control circuit 6.
The horizontal driver circuit 5 is operated when supplied with the adjusted voltage VK from the regulating circuit 3. The horizontal driver circuit 5 generates a horizontal transfer clock signal Øh, an output clock signal Øo, and a reset clock signal Ør, provides the horizontal transfer clock signal Øh to the horizontal transfer section 1h, and provides the output clock signal Øo and the reset clock signal Ør to the output section 1d. The horizontal transfer clock signal Øh, the output clock signal Øo, and the reset clock signal Ør are generated in synchronism with the horizontal synchronization signal VT.
The timing control circuit 6 includes a plurality of counters for counting a reference clock signal CK, which has a constant cycle. The timing control circuit 6 divides the reference clock signal CK at a predetermined timing to generate the vertical synchronization signal VT and the horizontal synchronization signal HT. The timing control circuit 6 provides a timing signal to a signal processing circuit (not shown), the boosting circuit 2, and the regulating circuit 3. The signal processing circuit performs a predetermined signal process on the signal output from the CCD image sensor 1. That is, the timing control circuit 6 synchronizes the operation of each circuit with the operational timing of the CCD image sensor 1.
FIG. 2 is a timing chart illustrating the operation of the imaging device 50 shown in FIG. 1. The frame transfer clock signal Øf is generated during a blanking period of the vertical synchronization signal VT. Thus, the information charges stored in the imaging section 1i during a predetermined storage time are simultaneously transferred to the storage section is at a high speed.
The vertical transfer clock signal Øv is generated in synchronism with the frame transfer clock signal Øf and in synchronism with the horizontal synchronization signal HT. Thus, a single image page of information charges, which are transferred from the imaging section 1i in accordance with the frame transfer clock signal Øf, is retrieved in the storage section 1s and sequentially transferred to the horizontal transfer section 1h in single line units. The horizontal transfer clock Øh is generated in synchronism with the horizontal synchronization signal HT during the period in which a single line of information charges is transferred from the storage section 1s. Thus, information charges transferred from the storage section 1s are sequentially output to the output section 1d in charge packet units.
FIG. 3 is a timing chart illustrating the operation of the output section 1d. The output clock signal Øo goes high in synchronism with the horizontal transfer clock signal Øh. In this state, a single packet of charges, which are transferred from the horizontal transfer section 1h, are retrieved in the floating diffusion of the output section 1d. The potential at the floating diffusion changes in accordance with the amount of stored charges. An output amplifier generates an image signal Y(t) in accordance with the potential change.
The image signal Y(t), which is generated in accordance with the period in which charges are stored in the floating diffusion, has a signal level corresponding to the luminance level of a subject image generated in a light receiving area. The reset clock signal Ør goes high at a timing delayed by a predetermined timing from when the information charges are retrieved in the floating diffusion. This retrieves the information charges stored in the floating diffusion in the reset drain and drains the information charges from the reset drain. The image signal Y(t) has a reset level during the period corresponding to the reset operation. Only the signal level is retrieved from the image signal Y(t), which repeats the signal level and the reset level, in the analog signal processing circuit in the next stage. The image signal Y(t) having only the signal level is further provided to an A/D conversion circuit and a digital signal processing circuit in the next stage.
The imaging device 50 is incorporated in an electronic device (e.g., cellular phone or notebook type personal computer) to function as a digital camera. To reduce power consumption of the entire electronic device, the imaging device 50 is provided with a standby mode in which the supply of power to the imaging device 50 is stopped when the camera function is not in use. In the standby mode, the power supply voltage VD is supplied to the boosting circuit 2 and the regulating circuit 3. However, the operations of the boosting circuit 2 and the regulating circuit 3 are stopped to cut the supply of operation voltage to the vertical driver circuit 4, the horizontal driver circuit 5, and the timing control circuit 6 in the next stage.
It is required that the power consumption of the imaging device 50 be reduced when the camera function is in use to further reduce power consumption of the electronic device. In addition to the imaging device 50, which is incorporated in the electronic device, the reduction in power consumption is also important in digital cameras, which are battery-driven.